1. Technical Field
The present invention relates to data-processing systems and, in particular, to a method and device in a data-processing system for reducing the signal propagation delay penalty associated with inserting a latch element in a circuit included within the system. Still more particularly, the present invention relates to an improved latch device where the output of the latch device is taken from a feedback circuit included within the latch element.
2. Description of the Related Art
In current data-processing systems, clock speeds of VLSI circuit chips are continually increasing. Engineers continue to search for methods to improve speed by reducing circuit delays. Each such improvement has a direct affect on chip performance.
One area that has plagued engineers is the cost associated with inserting latches, or flip-flops, in the chip design. Latches are necessary and essential to create devices such as instruction/execution pipelines in microprocessors, general purpose state-machines and other devices. Without these latches, creation of these devices would be impossible. In order to design VLSI chips, insertion of latches is necessary.
However, a signal propagation delay penalty is associated with the insertion of a latch on the overall performance of the chip. Typically, the signal propagation delay penalty for inserting a latch is approximately 5% of the overall chip cycle time.
FIG. 1 is a schematic diagram of a typical D-type latch, also called a D-type flip-flop, in accordance with the prior art. The data is input into the transmission gate 1 on an input signal line and appears an output signal line after passing through an inverter 2 and an inverter 3 when the clock signal is high. The circuit receives both a clock signal and the complement of the clock signal utilizing inverter 8. Each signal going through this latch must pass through transmission gate 1 and the two inverters 2, 3 before arriving at the output 9. Transistors 5 and 6 act as a switch, while transistors 4 and 7 act as an inversion unit.
For example, in order to create a state machine, at least two latches are required. The total signal propagation delay penalty then climbs to 10%. Typically, a state machine will be comprised of many latches, thus increasing the signal propagation delay penalty associated with the insertion of these latches in the state machine. As cycle times of current microprocessors reach the one nanosecond range, the latch insertion signal propagation delay penalty becomes significant.
Therefore, a need exists for a method and system for reducing the signal propagation delay penalty associated with inserting a latch in an integrated circuit.